In recent years, the storage capacity of semiconductor memory devices, represented by a DRAM (Dynamic Random Access Memory), has increased. It is increasingly demanded that these devices can operate at higher speeds. The increase in storage capacity has been achieved by making memory cells smaller and by increasing the chip size. However, the miniaturization of memory cells is physically limited, and the increase in chip size leads to a reduction of yield and impairs an increase of operating speed.
To solve these problems fundamentally, there has been proposed a method such that a core unit having memory cells and an interface unit having peripheral circuits to the memory cells are provided as chips that are independent of each other, and a plurality of core chips can be allocated to one interface chip (see Japanese Patent Application Laid-open No. 2004-327474). This can greatly decrease the size of each chip. In view of this, the method is expected to increase the storage capacity of semiconductor memory devices even more, while preserving high yield of the semiconductor memory devices.
Assume that the core unit and the interface unit are separate chips. The core chip and the interface chip can be fabricated in a memory process and a logic process, respectively. Generally, transistors made in the logic process can operate at higher speed than the transistors made in the memory process. Hence, if the interface chip is manufactured in the logic process, it can operate faster than the conventional interface chips. As a result, the interface chip enables the semiconductor memory device incorporating it to operate at high speed. Furthermore, the operating voltage of the interface chip can be lowered by about 1V, which helps to reduce the power consumption in the semiconductor memory device.
FIG. 18 is a schematic sectional view showing the structure of a conventional semiconductor memory device.
As shown in FIG. 18, the conventional semiconductor memory device includes an interposer substrate 10, an interface chip 20, and a plurality of core chips 31 to 34 (four core chips, for example). The interface chip 20 is provided on one surface 10a of the interposer substrate 10. The core chips 31 to 34 are mounted on the interface chip 20 one on another. The device gives and receives signals to and from an external device through external terminals 11. The exchange of signals between the interface chip 20 and the core chips 31 to 34 is performed through internal terminals 40 provided on the interface chip 20 and the core chips 31 to 34, and through electrodes 41 penetrating the provided on the interface chip 20 and the core chips 31 to 34. In this semiconductor memory device, the signals received through the internal terminals have greater widths than the signals received through the external terminals 11. The interface chip 20 changes the widths of the signals.
More specifically, the signals (addresses, commands, write data or the like) output from an external circuit via the external terminals 11 are supplied to the interface chip 20, expanded by the interface chip 20 in terms of signal width, and supplied to the core chips 31 to 34. Conversely, the signals (read signals or the like) output from the core chips 31 to 34 are supplied to the interface chip 20, compressed by the interface chip 20 in terms of signal width, and output via the external terminals 11 provided on the interposer substrate 10. Thus, the device can greatly increase the band width of signals to supply and receive to and from logic circuits such as CPUs that operate at high speed, although unable to perform large-scale parallel processing in corporation with the memory cores such as DRAMs that operate at low speed.
Semiconductor memory devices, such as DRAMs, are available in various specifications, even though they are of the same type. They differ in the width of input and output data (e.g., the difference between ×8 model and ×16 model), in clock frequency (e.g., the difference between 200 MHz model and 266 MHz model). This difference in the specifications comes mainly from the circuit configuration of the interface chip 20. The conventional semiconductor memory devices cannot changed in specification once the layers have been laid one on another, because the interface chip 20 and the core chips 31 to 34 are mounted, at a time, on the interposer substrate 10. Inevitably, they cannot be flexibly manufactured on demand to meet the customers' needs.
To solve this problem, the interface chip 20 and the core chips 31 to 34 can be stocked in great quantities, not laid one on another, until the specification of the semiconductor memory device to manufacture is formulated. However, this method is disadvantageous in that bare chips, i.e., chips not encapsulated yet, possibly remain long exposed to external conditions. In particular, core chips probably become defective if exposed to the external conditions for a long time. If they are stocked in large quantities and not encapsulated, they may degrade the reliability of the semiconductor memory devices, i.e., final products incorporating them.